The present invention relates generally to communication and signal processing systems, and more particularly, to a system that implements precision resampling that changes the sample rate of a sampled data signal, while maintaining the frequency coherence of the sampled signal.
A problem that occurs in communication and signal processing systems is changing the sample rate of a digital signal. An input signal is sampled at a rate that is established in an input circuit, such as a receiver for a communication signal. Based on other information, it is desired to change the sample frequency of the signal. The result is a process shown in FIG. 1. FIG. 1 illustrates a conventional resampler 10 that implements a resampler function that changes the sample rate of digital signals.
In the past, resampling has been accomplished by converting the signal to analog form with a digital to analog converter, then reconverting the signal to digital form with an analog-to-digital converter. This technique suffers from well-known problems relating to linearity and filtering of digital-to-analog converters and analog-to-digital converters.
Another technique that has been used in the past that maintains the signals as digital signals uses a digital resampling filter. The resampling filter is effectively a processor that upsamples the signal by a large amount, then downsamples the signal to a desired output clock frequency. The filter does not compute all of the upsampled signal values, only those that are to be used at the output. The effect is a filter with a large number of sets of coefficients. Each set of coefficients corresponds to a phase shift of the output clock compared to the input clock for a particular output sample.
A technique that has been used in the past to select the phase of the output sample has been a feedback loop 16 around a resampling filter 11 as is shown in FIG. 2. The resampler 10 shown in FIG. 2 includes the resampling filter 11 whose output is sent to a first-in, first-out (FIFO) buffer 12. A half-full signal is coupled to a phase control circuit 13 that advances the phase of the samples taken by the resampling filter 11. A reference frequency is input to an output clock synthesis circuit 14 that clocks the FIFO 12 to output the resampled data and outputs a resampled clock signal.
In operation, the FIFO buffer 12 is filled half full with samples from the resampling filter 11. When the FIFO buffer 12 is more than half full, the phase of the output samples is advanced by the phase control circuit 13, slowing the output of samples from the resampling filter 11. When the FIFO buffer 12 is less than half full, the phase of the resampling filter 11 is retarded, speeding the output of samples from the resampling filter 11.
The difficulty with this operation is that the feedback loop 16 is a very simple loop that drives the sample rate from the interpolating filter either higher or lower. The result is a limit cycle when operation has stabilized. The limit cycle causes the frequency of a sine wave at the input to be shifted first higher then lower. When precision operation is desired, this instability of the output frequency is not tolerable.
It would therefore be desirable, and it is an objective of the present invention to provide a system that implements precision resampling of a sampled data signal that changes the sample rate of the sampled data signal, while maintaining the frequency coherence of the sampled signal.
To accomplish the above and other objectives, the present invention provides for a system that implements precision resampling that changes the sample rate of a sampled data signal, while maintaining the frequency coherence of the sampled signal. A precision phase calculation for the relation between an input clock and an output clock enables the precision resampling.
An exemplary precision resampling system comprises a frequency measurement circuit that processes a data clock signal and a reference frequency signal to generate an estimate of the input sample rate of the data clock signal. A phase control circuit processes the estimate of the input sample rate and the reference frequency signal to generate an interpolation control signal. An output clock synthesis circuit processes the reference frequency signal to generate a resampled clock signal. An interpolation filter processes data samples, the data clock signal and the interpolation control signal to generate resampled data in response thereto and wherein the phase of the output samples is controlled by the interpolation control signal. A first-in, first-out buffer outputs the resampled data and the resampled clock signal.